FPGA to VGA with VHDL

The following code was inspired by the very good example of the youtube-user “Toni T800”

I use the VGA-mode 800×600@72Hz because I can directly use the 50MHz-clock as pixel-clock. At the end a green rectangle is displayed on the monitor. Next I need to display text as well, but for that I need to learn a lot more.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
ENTITY VGA IS
PORT(
	CLOCK_50: IN STD_LOGIC;
	VGA_HS, VGA_VS: OUT STD_LOGIC;
	VGA_R, VGA_G, VGA_B: OUT STD_LOGIC
);
END VGA;
 
ARCHITECTURE MAIN OF VGA IS
 
COMPONENT SYNC IS
PORT(
	CLK: IN STD_LOGIC;
	HSYNC, VSYNC: OUT STD_LOGIC;
	R, G, B: OUT STD_LOGIC
);
END COMPONENT SYNC;
 
BEGIN
C1: SYNC PORT MAP (CLOCK_50, VGA_HS, VGA_VS, VGA_R, VGA_G, VGA_B);
 
END ARCHITECTURE MAIN;

and the component

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
ENTITY SYNC IS
PORT(
	CLK: IN STD_LOGIC;
	HSYNC, VSYNC: OUT STD_LOGIC;
	R, G, B: OUT STD_LOGIC
);
END SYNC;
 
ARCHITECTURE MAIN OF SYNC IS
SIGNAL HPOS: INTEGER RANGE 0 TO 1040:=0;
SIGNAL VPOS: INTEGER RANGE 0 TO 666:=0;
BEGIN
 
PROCESS(CLK)
BEGIN
	IF (rising_edge(CLK)) THEN
		-- add 240 horiz. FP, BP, SYNC and 66 vert. FP, BP, SYNC
		-- display a green rectangle in the middle of the screen
		IF ((HPOS>440 AND HPOS<840 AND VPOS=216) OR 
			((HPOS=440 OR HPOS=840) AND (VPOS>216 AND VPOS<516)) OR 
			(HPOS>440 AND HPOS<840 AND VPOS=516)) THEN
			R<='0';
			G<='1';
			B<='0';
		ELSE
			R<='0';
			G<='0';
			B<='0';
		END IF;
 
		IF (HPOS<1040) THEN
			HPOS<=HPOS+1;
		ELSE
			HPOS<=0;
			IF (VPOS<666) THEN
				VPOS<=VPOS+1;
			ELSE
				VPOS<=0;
			END IF;
		END IF;
 
		IF (HPOS>56 AND HPOS<176) THEN
			HSYNC<='0';
		ELSE	
			HSYNC<='1';
		END IF;
 
		IF (VPOS>0 AND VPOS<43) THEN -- maybe 37>x<43
			VSYNC<='0';
		ELSE	
			VSYNC<='1';
		END IF;
 
		IF ((HPOS>0 AND HPOS<240) OR (VPOS>0 AND VPOS<66)) THEN
			R<='0';
			G<='0';
			B<='0';
		END IF;
	END IF;
END PROCESS;
 
END ARCHITECTURE MAIN;

I used the following GPIO-pins of the Altera Cyclone IV, because so I don’t need to separate the dupont cable. All pins are located together on the DE0-Nano board.
pin_planner
The following images shows the result after programming the FPGA.
IMG_0008
And here you can see the connection between the FPGA and the monitor via the self-etched adaptor-board.
IMG_0010

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